1. Field of the Invention
The present invention relates to a peak hold circuit, and particularly relates to a current mode peak hold circuit wherein output current corresponding to the peak value of input current can be obtained even for input currents with little change in magnitude, at essentially higher speeds.
2. Description of the Related Art
An example of a conventionally-known peak hold circuit wherein output voltage corresponding to peak values of input voltage can be obtained is shown in FIG. 25. The voltage of the non-inverting input terminals of an operational amplifier 2502 (equal to the voltage VH held by a capacitor 2507) is initially equal to the voltage VIN1 of the non-inverting input terminals of an operational amplifier 2501.
Thus, the voltage of the output terminal of the operational amplifier 2502, the voltage of the inversion input terminal of the operational amplifier 2501, and the voltage of the output terminal of the operational amplifier 2501 are VH which is VIN1, the voltage at both ends of the diodes 2503 and 2504 are zero, with the diodes 2503 and 2504 being in a non-conducting state.
In this state, even in the event that the voltage of the input terminal 2508 rises and reaches VIN2, the diode 2503 is in a non-conducting state, so the output voltage of the operational amplifier 2501 rises greatly regardless of the negative feedback. Then, when forward voltage is applied to the diode 2504 an the diode 2504 is in a conducting state, the capacitor 2507 is charged, the voltage at both ends of the capacitor 2507 rises, and in the same manner, the voltage of the output terminal 2509 of the operational amplifier 2502 and the voltage of the inverted input terminals of the operational amplifier 2503 rise.
Then, at the point that the voltage at both ends of the capacitor 2507 is equal to the voltage VIN2 of the output terminal 2509 of the operational amplifier 2501, the diode 2504 enters a non-conducting state, and consequently, the voltage VIN2 is held by the capacitor 2507.
In the event that the voltage of the input terminals 2508 drops and changes from VIN2 to VIN3 in this state, while the output voltage of the operational amplifier 2501 drops, the voltage at both ends of the capacitor 2507 (i.e., the held voltage VH) is VIN2, so inverse voltage is applied to both ends of the diode 2504, so the diode 2504 remains in a non-conducting state, and the held voltage VH remains unchanged at VIN2.
Thus, voltage corresponding to the peak value of he input voltage of the input terminals 2508 is output at the output terminal 2509.
However, such voltage mode peak hold circuits are configured of multiple operational amplifiers, diodes, capacitors, and so forth, so the circuit tends to become large in size.
Also, the circuit is arranged so as to make input to the peak hold circuit shown in FIG. 25 following converting the input current into voltage values with a current/voltage converting circuit, so there is a limit to how far the size of the circuit can be reduced, and the circuit has not been able to be reduced in size any further.
A known example of a peak hold circuit which has solved such problems is described in Japanese Patent Application No. 10-5449. This peak hold circuit is known as a current mode peak hold circuit, and has a configuration such as shown in FIG. 26.
FIG. 26 will now be described. This current mode peak hold circuit is configured of P-MOS transistors 2601 and 2602, an NPN transistor 2603, and a PNP transistor 2607. The gates of the P-MOS transistors 2601 and 2602 are connected in common, and the sources are connected to the electric power source VDD. The P-MOS transistor 2601 has the drain thereof connected to the terminal 2604, and the NPN transistor 2602 has the drain thereof connected to the terminal 2606. The collector of the NPN transistor 2603 is connected to the gates of the P-MOS transistor 2601 and 2602 connected in common, the emitter thereof is connected to the drain of the P-MOS transistor 2601, and the base is connected to a reference potential VBIAS1. The emitter of the PNP transistor 2607 is connected to the drain of the P-MOS 26501, the base the base is connected to a reference potential VBIAS2, and the collector is grounded.
The reference potential VBIAS1 and the reference potential VBIAS2 are lower than the voltage of the electric power source VDD but higher than the ground potential, are a potential such that the NPN transistor 2603 and the PNP transistor 2607 do not turn on simultaneously, and the difference potential between the reference potential VBIAS1 and the reference potential VBIAS2 is 0.7 V, for example.
In FIG. 26, V4(t) represents the absolute potential of the terminal 2604 at time t, iD1(t) represents the drain current of the P-MOS transistor 2601 at time t, iin(t) represents input current at time t, and iout(t) is output current at time t, with the direction of the arrows being the forward direction for each. Note that iout(t) matches the drain current of the P-MOS transistor 2602.
(1) Let us say that the P-MOS transistor 2601 is operated at saturation range, and the drain current iD1(t) and input current iin(t) of the P-MOS transistor 2601 match. In this state, the potential of the terminal 2604 is generally the average potential of the two reference potentials VBIAS1 and VBIAS2, the voltage between the base and emitter of the NPN transistor 2603 and PNP transistor 2607 are both around 0.35 V, and both the NPN transistor 2603 and PNP transistor 2607 are in the cut-off state.
In the event that the input current iin(t) increases over a period from time t0 to time t1 as shown in FIG. 27A for example, the relation between the drain current iD1(t) and input current iin(t) of the P-MOS transistor 2601 becomes that represented by iD1(t) less than iin(t), and the voltage of the terminal 2604 drops.
The PNP transistor 2607 maintains the cut-off state, but at the point that the voltage of the terminal 2604 drops around 0.5 V as to the reference potential VBIAS1, the NPN transistor 2603 enters the forward activation range and begins to cause current to flow, and at the point that the voltage of the terminal 2604 drops around 0.7 V as to the reference potential VBIAS1, the NPN transistor 2603 turns on.
At the point that the NPN transistor 2603 turns on, the difference current between the input current and the drain current iD1(t) of the P-MOS transistor 2601, i.e., iin(t)xe2x88x92iD1(t), flows from the node 2605 to the terminal 2604 via the NPN transistor 2603, and the voltage of the node 2605 drops so that the input current iin(t) and the drain current iD1(t) of the P-MOS transistor 2601 are equal. The voltage drop of this node 2605 is generated by charge being extracted from the parasitic capacity between the gate sources of the P-MOS transistors 2601 and 2602 connected to the node 2605, via the NPN transistor 2603. At this time, the peak hold circuit shown in FIG. 26 acts as a current mirror circuit, and output current proportionate to the input current is obtained (see FIG. 27B).
(2) In the event that the increase of the input current iin(t) stops over a period from time t1 to time t2 as shown in FIG. 27A for example, iD1(t) =iin(t), and the NPN transistor 2603 and PNP transistor 2607 are both in the cut-off state, so the voltage of the terminal 2604 rises, and the voltage of the terminal 2604 settles down at around the average potential of the two reference potentials VBIAS1 and VBIAS2. At this time, the node 2605 is in a high-impedance state, so the charge at time t1 at the parasitic capacity between the gate sources of the P-MOS transistors 2601 and 2602 does not change.
On the other hand, the voltage between the gate sources of the P-MOS transistors 2601 and 2602 is maintained at VGS(t1), and output current iout(t) proportionate to the input current iin(t1) at time t1 is maintained (see FIG. 27B).
(3) In the event that the input current iin(t) at time t is smaller than the input current iin(t1) at time t1 in a period from time t2 to time t3 as shown in FIG. 27A for example, voltage of the terminal 2604 further rises, but the NPN transistor 2603 maintains the cut-off state, so the voltage VGS(t1) between the gate sources of the P-MOS transistors 2601 and 2602 is maintained, and the value of the output current iout(t) at time t1 is maintained. Then, at the point that the voltage of the terminal 2604 rises around 0.7 V as to the reference potential VBIAS2, the PNP transistor 2607 enters the forward activation range and turns on, and the difference current between the drain current iD1(t) of the P-MOS transistor 2601 and the input current, i.e., iD1(t)xe2x88x92iin(t), in other words the difference current between the input current at time t1 and the input current at time t, i.e., iin(t1)xe2x88x92iin(t), flows.
(4) In the event that current exceeding the current iin(t1) at time t1 is input in a period from time t3 to time t4 as shown in FIG. 27A for example, and the current continues to increase, the voltage of the terminal 2604 drops, and at the point that the voltage of the terminal 2604 drops around 0.5 V as to the reference potential VBIAS1, the NPN transistor 2603 enters the forward activation range again and begins to cause current to flow, and at the point that the voltage of the terminal 2604 drops around 0.7 V as to the reference potential VBIAS1, the NPN transistor 2603 turns on.
At the point that the NPN transistor 2603 turns on, the difference current between the input current and the drain current iD1(t) of the P-MOS transistor 2601, i.e., iin(t)xe2x88x92iD1(t), flows from the node 2605 via the NPN transistor 2603, and the voltage of the node 2605 drops so that the input current iin(t) and the drain current iD1(t) of the P-MOS transistor 2601 are equal.
Thus, output current iout(t) corresponding to the peak value of the input current iin(t) is obtained.
On the other hand, a current mode peak hold circuit co the configuration shown in FIG. 28 is known. The current mode peak hold circuit shown in FIG. 28 is an arrangement wherein conductor types of the components corresponding to those of the current mode peak hold circuit shown in FIG. 26 are reversed, and is configured of N-MOS transistors 2811 and 2812, a PNP transistor 2813, and an NPN transistor 2817.
The gates of the N-MOS transistors 2811 and 2812 are connected in common, the sources are grounded, the N-MOS transistor 2811 has the drain thereof connected to the terminal 2814, and the N-MOS transistor 2812 has the drain thereof connected to the terminal 2816. The collector of the PNP transistor 2813 is connected to the gates of the N-MOS transistor 2811 and 2812 connected in common, the emitter thereof is connected to the drain of the N-MOS transistor 2811, the base is connected to the reference potential VBIAS1. The emitter of the NPN transistor 2817 is connected to the drain of the N-MOS transistor 2811, the base is connected to the reference potential VBIAS2, and the collector thereof is connected to the electric power source VDD.
The reference potential VBIAS1 and the reference potential VBIAS2 are lower than the potential of the electric power source VDD but higher than the ground potential, are a potential such that the NPN transistor 2813 and the PNP transistor 2817 do not turn on simultaneously, and the difference potential between the reference potential VBIAS1 and the reference potential VBIAS1 is 0.7 V, for example.
In FIG. 28, V14(t) represents the absolute potential of the terminal 2814 at time t, iD11(t) represents the drain current of the N-MOS transistor 2811 at time t, iin(t) represents input current at time t, and iout(t) is output current at time t, with the direction of the arrows being the forward direction for each. Note that the output current iout(t) matches the drain current of the N-MOS transistor 2812.
(1) Let us say that the N-MOS transistor 2811 is operated at saturation range, and the drain current iD11(t) and input current iin(t) of the N-MOS transistor 2811 match, the potential of the terminal 2814 is generally the average potential of the two reference potentials VBIAS1 and VBIAS2, the voltage between the base and emitter of the PNP transistor 2813 and NPN transistor 2817 are both around 0.35 V, and both the PNP transistor 2813 and NPN transistor 2817 are in the cut-off state.
(2) In the event that the input current iin(t) increases over a period from time t0 to time t1 as shown in FIG. 29A for example, the relation between the drain current iD11(t) and input current iin(t) of the N-MOS transistor 2811 becomes that represented by iD11(t) less than iin(t), so the voltage of the terminal 2814 rises. At this time, while the NPN transistor 2817 maintains the cut-off state, but at the point that the voltage of the terminal 2814 rises around 0.5 V as to the reference potential VBIAS1, the PNP transistor 2813 enters the forward activation range and begins to cause current to flow, and at the point that the voltage of the terminal 2814 rises around 0.7 V as to the reference potential VBIAS1, the PNP transistor 2813 turns on.
The current iin(t)xe2x88x92iD11(t) flows to the node 2815 via the PNP transistor 2813 so that iin(t) and iD11(t) match, and the voltage of the node 2815 rises.
The voltage of this node 2815 rises due to charge being supplied to the parasitic capacity between the gate sources of the N-MOS transistors 2811 and 2812 connected to the node 2815, via the PNP transistor 2813. At this time, the peak hold circuit shown in FIG. 28 acts as a current mirror circuit, and output current proportionate to the input current is obtained.
(3) In the event that the increase of iin(t) stops over a period from time t1 to time t2, iD11(t)=iin(t), and the voltage of the terminal 2814 drops so that both PNP transistor 2813 and NPN transistor 2817 reach cut-off, and settles down at around the average potential of the two reference potentials VBIAS1 and VBIAS2. At this time, the node 2815 is in a high-impedance state, so the charge at time t1 does not change, and the voltage between the gate sources of the M-MOS transistors 2811 and 2812 is maintained at VGS(t1). Here, the output current iout(t) is maintained at a current proportionate to the input current iin(t1) at time t1.
(4) In the event that the input current iin(t) at time t is smaller than the input current iin(t1) in a period from time t2 to time t3, voltage of the terminal 2814 further drops, but the PNP transistor 2813 maintains the cut-off state, so VGS(t1) is maintained, and output current iout(t) maintains the value at time t1. At this time, in the event that the voltage of the terminal 2814 drops around 0.7 V as to the reference potential VBIAS2, the NPN transistor 2817 enters the forward activation range and turns on, and a current of iD(t)xe2x88x92iin(t), i.e., iin(t1)xe2x88x92iin(t), flows.
(5) In the event that current exceeding the input current iin(t1) at time t1 is input in a period from time t3 to time t4, and the current continues to increase, the voltage of the terminal 2814 rises, and at the point that the voltage of the terminal 2814 rises around 0.5 V as to the reference potential VBIAS1, the PNP transistor 2813 enters the forward activation range again and begins to cause current to flow, and at the point that the voltage of the terminal 2814 rises around 0.7 V the PNP transistor 2813 turns on.
Then, the current iin(t)xe2x88x92iD11(t) flows to the node 2815 via the PNP transistor 2813, and the voltage of the node 2815 rises so that iin(t) and iD11(t) are equal. Thus, output voltage iout(t) corresponding to the input current iin(t) is obtained. Accordingly, output current corresponding to the peak value of the input current is obtained at the output terminal 2816.
However, in the event that operating the peak hold circuit shown in FIG. 26 with little change in magnitude at higher speeds is attempted, the following problems have occurred.
As described above, the voltage V4(t) of the terminal 2604 repeats rising and dropping according to the input current, and under the above-described bias conditions, the change in voltage thereof is around 0.7 V, as shown in FIG. 30.
On the other hand, there is parasitic capacity at the terminal 2604 such as junction capacitance of the connected devices, so charging and discharging to this parasitic capacity must be performed in order for the terminal 2604 to perform the above-described voltage change, and the charge for charging and discharging is supplied by the difference current between the input current iin(t) and the held current, i.e., with the drain current iD11(t) of the N-MOS transistor 2601.
Accordingly, in the event that the magnitude of change of the input current is small and the speed is high, sufficient charge necessary for voltage fluctuations is not supplied to the parasitic capacity of the terminal 2604, and the peak holding action does not work.
On the other hand, when attempting to operate the peak hold circuit shown in FIG. 28 with a small magnitude of change of the input current at higher speeds, the following problems have resulted.
As described above, the voltage V14(t) of the terminal 2814 repeats rising and dropping according to the input current, and under the above-described bias conditions, the fluctuation in voltage thereof is around 0.7 V, as shown in FIG. 31.
On the other hand, there is parasitic capacity added at the terminal 2814 such as junction capacitance of the connected devices, so charging and discharging to this parasitic capacity must be performed in order for the terminal 2814 to perform the above-described voltage fluctuations, and the charge for charging and discharging is supplied by the difference current between the input current iin(t) and the held current, i.e., with the drain current iD11(t) of the N-MOS transistor 2811.
Accordingly, in the event that the magnitude of change of the input current is small and the speed is high, sufficient charge necessary for voltage fluctuation is not supplied to the parasitic capacity of the terminal 2814, and the peak holding action does not work.
Accordingly, it is an object of the present invention to solve the above-described problems, and to provide a current mode peak hold circuit wherein output current corresponding to the peak value of input current can be obtained even for input currents with little change in magnitude, at essentially higher speeds.
The peak hold circuit according to a first aspect of the present invention comprises: a current mirror circuit for generating a first constant-current source for causing flow of a current that is the same magnitude as an input current from an input terminal, and a second constant-current source for causing flow of a current that is the input current multiplied by a predetermined multiplication factor; a first FET wherein the drain thereof is connected to the first constant-current source and the source thereof is connected to a first electric power source; a second FET wherein the drain thereof is connected to an output terminal and the source thereof is connected to the first electric power source and the gate thereof is connected in common with the gate of the first FET; a two-stage serial circuit comprising first and second transistors having complementary properties, provided between the gates connected in common and a second electric power source which has lower voltage than the first electric power source, wherein the nodes of the first and second transistors are connected to the drain of the first FET; current detecting means for detecting the drain current of the first FET; and applied voltage control means which compare a current which is a drain current detected by the current detecting means multiplied by the predetermined multiplication factor, with a current which is the input current from the second constant-current source multiplied by the predetermined multiplication factor, and applies a first applied voltage which is lower than voltage of the first electric power source to the first transistor, and also applies to the second transistor a second applied voltage which is constantly lower than the first applied voltage by a predetermined voltage wherein the first and second transistors are not simultaneously turned on, wherein, in the event that the detected current detected by the current detecting means is greater than the drain current of the first FET, the first voltage is applied as the first applied voltage to the first transistor so as to turn the first transistor on, and the second voltage is applied as the second applied voltage to the second transistor so as to turn the second transistor off, and in the event that the detected current is smaller than the drain current, a third voltage lower by the first voltage by a predetermined voltage is applied as the first applied voltage to the first transistor so as to turn the first transistor off, and a fourth voltage lower by the second voltage by a predetermined voltage is applied as the second applied voltage to the second transistor so as to turn the second transistor on, and further in the event that the detected current is equal to the drain current, an averaged voltage of the first voltage and the third voltage is applied as the first applied voltage to the first transistor so as to turn the first transistor off, and an averaged voltage of the second voltage and the fourth voltage is applied as the second applied voltage to the second transistor so as to turn the second transistor off.
A capacitor for holding charge may be connected between the gates of the first and second FETs connected in common and the first electric power source. The peak hold circuit may also further comprise switching means for setting the potential of the gates of the first and second FETs connected in common to the potential of the first electric power source.
Also, the first and second FETs may be P-MOS FETs, the first transistor may be an NPN transistor, and the second transistor may be a PNP transistor. Or, the first and second FETs may be P-MOS FETs, the first transistor may be an N-MOS transistor, and the second transistor may be a P-MOS transistor.
The peak hold circuit according to a second aspect of the present invention comprises: a current mirror circuit for generating a first constant-current source for causing flow of a current that is the same magnitude as an input current to an input terminal, and a second constant-current source for causing flow of a current that is the input current multiplied by a predetermined multiplication factor; a first FET wherein the drain thereof is connected to the first constant-current source and the source thereof is connected to a second electric power source with lower voltage than a first electric power source; a second FET wherein the drain thereof is connected to an output terminal and the source thereof is connected to the second electric power source and the gate thereof is connected in common with the gate of the first FET; a two-stage serial circuit comprising first and second transistors having complementary properties, provided between the gates connected in common and the first electric power source, wherein the nodes of the first and second transistors are connected to the drain of the first FET; current detecting means for detecting the drain current of the first FET; and applied voltage control means which compare a current which is a drain current detected by the current detecting means multiplied by the predetermined multiplication factor, with a current which is the input current from the second constant-current source multiplied by the predetermined multiplication factor, and applies a first applied voltage which is higher than voltage of the second electric power source to the first transistor, and also applies to the second transistor a second applied voltage which is constantly higher than the first applied voltage by a predetermined voltage wherein the first and second transistors are not simultaneously turned on, wherein, in the event that the detected current detected by the current detecting means is greater than the drain current of the first FET, the first voltage is applied as the first applied voltage to the first transistor so as to turn the first transistor on, and the second voltage is applied as the second applied voltage to the second transistor so as to turn the second transistor off, and in the event that the detected current is smaller than the drain current, a third voltage higher than the first voltage by a predetermined voltage is applied as the first applied voltage to the first transistor so as to turn the first transistor off, and a fourth voltage higher than the second voltage by a predetermined voltage is applied as the second applied voltage to the second transistor so as to turn the second transistor on, and further in the event that the detected current is equal to the drain current, an averaged voltage of the first voltage and the third voltage is applied as the first applied voltage to the first transistor so as to turn the first transistor off, and an averaged voltage of the second voltage and the fourth voltage is applied as the second applied voltage to the second transistor so as to turn the second transistor off.
A capacitor for holding charge may be connected between the gates of the first and second FETs connected in common and the second electric power source. The peak hold circuit may further comprise switching means for setting the potential of the gates of the first and second FETs connected in common to the potential of the second electric power source.
Also, the first and second FETs may be N-MOS FETs, the first transistor may be a PNP transistor, and the second transistor may be an NPN transistor. Or, the first and second FETs may be N-MOS FETs, the first transistor may be a P-MOS FET, and the second transistor may be an N-MOS FET.
Further objects, features and advantages of the present invention will become apparent from the following description of the preferred embodiments with reference to the attached drawings.